M16CSLASH62M datasheet(488/615 Pages) RENESAS

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Multiple Interrupts

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-171

2.14.2 Multiple Interrupts Operation

The state when control branched to an interrupt routine is described below:

· The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled).

· The interrupt request bit of the accepted interrupt is set to “0”.

· The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as as

signed to the accepted interrupt.

Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request as-

signed a priority higher than the IPL to be accepted.

An interrupt request that is not accepted because of low priority will be held. If the condition following is

met when the REIT instruction returns the IPL and the interrupt priority is determined, then the interrupt

request being held is accepted.

Interrupt priority level of the interrupt request being held

Returned the IPL

Figure 2.14.6 shows the example of the multiple interrupts operation.

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