M16CSLASH62M datasheet(483/615 Pages) RENESAS

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Multiple Interrupts

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-166

Figure 2.14.1. Memory map of the interrupt control registers

004416

004516

004616

004716

004816

004916

004A16

004B16

004C16

004D16

004E16

004F16

005016

005116

005216

005316

005416

005516

005616

005716

005816

005916

005A16

005B16

005C16

005D16

005E16

005F16

INT1 interrupt control register (INT1IC)

Timer B0 interrupt control register (TB0IC)

Timer B2 interrupt control register (TB2IC)

Timer A1 interrupt control register (TA1IC)

Timer A3 interrupt control register (TA3IC)

UART0 transmit interrupt control register (S0TIC)

INT2 interrupt control register (INT2IC)

INT0 interrupt control register (INT0IC)

Timer B1 interrupt control register (TB1IC)

Timer A0 interrupt control register (TA0IC)

Timer A2 interrupt control register (TA2IC)

Timer A4 interrupt control register (TA4IC)

UART0 receive interrupt control register (S0RIC)

UART1 transmit interrupt control regster(S1TIC)

UART1 receive interrupt control register(S1RIC)

DMA1 interrupt control register (DM1IC)

DMA0 interrupt control register (DM0IC)

Key input interrupt control register(KUPIC)

A-D conversion interrupt control register (ADIC)

Bus collision detection interrupt control register (BCNIC)

UART2 transmit interrupt control register (S2TIC)

UART2 receive interrupt control register (S2RIC)

INT3 interrupt control register (INT3IC)

Timer B5 interrupt control register (TB5IC)

Timer B3 interrupt control register (TB3IC)

Timer B4 interrupt control register (TB4IC)

SI/O4 interrupt control register (S4IC)

INT5 interrupt control register (INT5IC)

SI/O3 interrupt control register (S4IC)

INT4 interrupt control register (INT4IC)

2.14 Multiple interrupts Usage

2.14.1 Overview of the Multiple interrupts usage

The following is an overview of the multiple interrupts usage.

(1) Interrupt control

Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the

priority to be accepted. What is described here does not apply to non-maskable interrupts.

Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority

level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or

absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level

select bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I

flag) and the IPL are located in the flag register (FLG).

Figure 2.14.1 shows the memory map of the interrupt control registers, and Figure 2.14.2 shows the

interrupt control registers.

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