M16CSLASH62M datasheet(425/615 Pages) RENESAS

425 / 615 page

SI/O3, 4

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-108

In transmitting data in this mode, choose functions from those listed in Table 2.6.1. Operations of the

circled items are described below. Figure 2.6.3 shows the operation timing, and Figures 2.6.4 and 2.6.5

show the set-up procedures.

2.6.2 Operation of SI/O3,4

(1) Transfer begins upon writing the SI/Oi transmit data.

The transmit data is sent out from the SOUTi pin synchronously with falling edges of the

transfer clock.

(2) When SOUT finishes sending one byte of data, the interrupt request bit is set to 1.

(3) After the transfer is completed, SOUT holds the last data for a 1/2 transfer clock period before

going to a high-impedance state.

• Do not write data to the SI/Oi transmit/receive register (i = 3, 4; addresses 036016, 036416)

during a transfer.

• Data can only be written to the SI/Oi transmit/receive register when the device is idle neither

sending nor receiving data.

Operation

Note

Table 2.6.1. Choosed functions

Item

Set-up

Transfer clock

source

Internal clock (f1 / f8 / f32)

External clock (CLKi pin)

SOUTi initial value

set function

Not used

Used

Transfer clock

LSB first

MSB first

Example of wiring

Figure 2.6.3. Operation timing of transmission in SI/O3, 4 mode

Example of operation

CLKi

SOUTi

CLK

SIN

Microcomputer

Receiver side IC

SI/Oi output

SOUTi

(3) High-

impedance

(i = 3, 4)

1.5 TCLK (Max)

Hi-Z

TCLK

Internal clock

(1) Transmission enabled

SI/Oi transmit/receive

CLKi

SI/Oi input

SINi

SI/Oi interrupt

request bit

TCLK = 2(n + 1) / fi

fi: frequency of BRGi count source (f1, f8, f32)

n: value set to SiBRG

Cleared to “0” when interrupt request is accepted, or cleared by software

"1"

"0"

(2) Transmission

is complete

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