M16CSLASH62M datasheet(410/615 Pages) RENESAS

410 / 615 page

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-93

UART

Example of wiring

Figure 2.5.14. Operation timing of transmission in UART mode (used for SIM interface)

Example of operation (when direct format)

Microcomputer

SIM card

TxD2

RxD2

Transmit

enable bit (TE)

Transmit buffer

empty flag (Tl)

Transmit buffer

empty flag

(TEXPT)

D0 D1

D2 D3 D4 D5 D6 D7

Start

bit

Parity

bit

The above timing applies to the following settings :

• Parity is enabled.

• One stop bit.

• Transmit interrupt cause select bit = “1”.

“0”

“1”

“0”

“1”

“0”

“1”

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f1, f8, f32)

n : value set to BRG2

Transmit

interrupt request

bit (IR)

“0”

“1”

Cleared to “0” when interrupt request is accepted, or cleared by software

D0 D1 D2 D3

D4 D5 D6

Shown in ( ) are bit symbols.

Transfer clock

Stop

bit

Since a parity error occurred, the

“L” level returns from TxD2

Detects the level

using an interrupt

routine

Detects the level

using an interrupt

routine

D0 D1

D2 D3 D4 D5 D6 D7

D0 D1 D2 D3

D4 D5 D6

TXD2 (Note 2)

RXD2 (Note 2)

Signal line level

(Note 2)

(1) Transmission enabled

(2) Start transmission

(3) Confirme stop bit

(4) Start transmission

(5) Dispose

parity error

Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.

Note 2: TxD2 and RxD2 are connected in the manner of wired OR as shown in the connection diagram. So TxD2 and RxD2 ought to

become the same signal from the logical standpoint, but the output signals turn complex, so they are shown separately. Also,

the signal level resulting from connecting TxD2 and RxD2 is shown as a signal line level.

Transferred from UART2 transmit buffer register to UART2 transmit register

Data is set in UART2 transmit buffer register

(Note 1)

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