M16CSLASH62M datasheet(392/615 Pages) RENESAS

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UART

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-75

(2) Transfer rate

The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans-

fer rate. The count source for the transfer rate register can be selected from f1, f8, f32, and the input

from the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU’s main clock by 1, 8, and 32

respectively.

Baud rate

(bps)

BRG's

count source

System clock : 16MHz

System clock : 7.3728MHz

BRG's set value : n

Actual time (bps)

BRG's set value : n

600

1200

2400

4800

9600

14400

19200

28800

31250

207 (CF16)

103 (6716)

51 (3316)

207 (CF16)

103 (6716)

68 (4416)

51 (3316)

34 (2216)

33 (2116)

601

1202

2404

4808

9615

14493

19231

28571

31250

95 (5F16)

47 (2F16)

23 (1716)

95 (5F16)

47 (2F16)

31 (1F16)

23 (1716)

15 (F16)

600

1200

2400

4800

9600

14400

19200

28800

Actual time (bps)

Table 2.5.2. Example of baud rate setting

Table 2.5.3. Error detection

Type of error

When the flag turns on

Description

How to clear the flag

• This error occurs when the

next data lines up before the

content of the UARTi receive

buffer register is read.

• The next data is written to the

UARTi receive buffer register.

• The UARTi receive interrupt

request bit does not change.

• This error occurs when the

stop bit falls short of the set

number of stop bits.

• With parity enabled, this error

occurs when the total number

of 1's in character bits and the

parity bit is different from the

specified number.

• This flag turns on when any

error (overrun, framing, or

parity) is detected.

The error is detected

when data is

transferred from the

UARTi receive register

to the UARTi receive

buffer register.

• Set the serial I/O mode select

bits to “0002”.

• Set the receive enable bit to

“0”.

• When all error (overrun,

framing, and parity) are

removed, the flag is cleared.

• Set the serial I/O mode select

bits to ”0002”.

• Set the receive enable bit to

“0”.

• Read the lower-order byte of

the UARTi receive buffer

Overrun error

Framing error

Parity error

Error-sum flag

(3) An error detection

In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.5.3.

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