M16CSLASH62M datasheet(341/615 Pages) RENESAS

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Timer A

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-24

Figure 2.2.18. Operation timing of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected

2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode,

multiply-by-4 mode selected)

In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table

2.2.7. Operations of the circled items are described below. Figure 2.2.18 shows the operation timing, and

Figure 2.2.19 shows the set-up procedure.

Table 2.2.7. Choosed functions

Item

Set-up

Count operation type

Reload type

Free run type

Processing 2 phase

pulses (Note)

Normal processing

4-multiplication processing

Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4-

multiplication processes.

(1) Setting the count start flag to “1” causes the counter to count effective edges of the count source.

(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count

continues. At this time, the interrupt request bit goes to “1”.

(3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count

continues. At this time, the interrupt request bit goes to “1”.

• The up count or down count conditions are as follows:

Operation

Note

Up count

Input signal to the

TAiOUT pin

Input signal to the

TAiIN pin

Down

count

Input signal to the

TAiOUT pin

Input signal to the

TAiIN pin

“H” level

“L” level

Rising

Falling

Rising

Falling

“L” level

“H” level

“L” level

Rising

Falling

Rising

“H” level

“L” level

Time

Set to “1” by software

000016

Count start flag

Timer Ai interrupt

request bit

“1”

“0”

“1”

“0”

FFFF16

TAiOUT

“H”

“L”

“H”

“L”

TAiIN

(1) Start count

(2) Underflow

(3) Overflow

Cleared to “0” when interrupt request is accepted, or cleared by software

Table 2.2.8. The up count or down count conditions

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