R8C13 datasheet(18/224 Pages) RENESAS

18 / 224 page

Rev.1.20

Jan 27, 2006

page 7 of 205

REJ09B0111-0120

R8C/13 Group

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and

FB comprise a register bank. Two sets of register banks are provided.

2.1 Data Registers (R0, R1, R2 and R3)

R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0

can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.

The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit

data register (R2R0). The same applies to R3R1 as R2R0.

Data registers(1)

Address registers(1)

Frame base registers(1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

NOTES:

1. A register bank comprises these registers. Two sets of register banks are provided

R0H(High-order of R0)

b15

b8 b7

INTBH

USP

ISP

IPL

R0L(Low-order of R0)

R1H(High-order of R1) R1L(Low-order of R1)

b31

b19

INTBL

b15

b19

b15

FLG

b15

Reserved bit

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

The 4-high order bits of INTB are INTBH and

the 16-low bits of INTB are INTBL.

Figure 2.1 CPU Register

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