R5F2L358ADFP datasheet(84/848 Pages) RENESAS

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5. Resets

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 48 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

Resets

The following resets are available: hardware reset, power-on reset, voltage monitor 0 reset, watchdog timer reset, and

software reset.

Table 5.1 lists the Reset Names and Sources and Figure 5.1 shows the Reset Circuit Block Diagram.

Figure 5.1

Reset Circuit Block Diagram

Table 5.1

Reset Names and Sources

Reset Name

Source

Hardware reset

The input voltage to the RESET pin is held low.

Power-on reset

VCC rises.

Voltage monitor 0 reset

VCC falls. (Monitor voltage: Vdet0)

Watchdog timer reset

Underflow of the watchdog timer

Software reset

Write 1 to the PM03 bit in the PM0 register.

RESET

Power-on reset

circuit

Voltage

detection

circuit

Watchdog

timer

CPU

Pins, CPU, and SFRs (1)

VCC

Hardware reset

Power-on reset

Voltage monitor 0 reset

Watchdog timer

reset

Software reset

Note:

1. The CWR bit in the RSTFR register is set to 0 (cold start-up) after power-on, voltage monitor 0 reset, or

exit from power-off mode. This bit remains unchanged at a software reset, watchdog timer reset, or

oscillation detection reset.

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