M32CSLASH86 datasheet(317/505 Pages) RENESAS

317 / 505 page

Page 294

22. Intelligent I/O (Communication Function)

)

(

Figure 22.25 G0ERC and G1ERC Registers

SI/O Expansion Receive Control Register i (i=0,1)(1)

Symbol

Address

After Reset

G0ERC, G1ERC

00FD16, 013D16

0016

Bit Name

Function

Bit

Symbol

NOTES:

1. The GiERC register is used in special communication mode or HDLC data processing mode.

It must be set to "0010 00002" in clock synchronous serial I/O mode.

It must be in a reset state or be set to "0016" in UART mode.

2. When the ACRC bit in the GiEMR register is set to "1" (CRC reset function used), set the CMP3E bit

to "1".

CMP0E

CMP1E

CMP2E

Data Compare

Function 0

Select Bit

CMP3E

RCRCE

RSHTE

RBSF0

RBSF1

Receive CRC

Enable Bit

Receive Shift

Operation

Enable Bit

0 : Not used

1 : Used

0 : Receive shift operation disabled

1 : Receive shift operation enabled

Data Compare

Function 1

Select Bit

Data Compare

Function 2

Select Bit

Data Compare

Function 3

Select Bit

Receive Bit

Stuffing "1" Delete

Select Bit

Receive Bit

Stuffing "0" Delete

Select Bit

0 : "1" is not deleted

1 : "1" is deleted

0 : "0" is not deleted

1 : "0" is deleted

0 : The GiDR register (receive data register) is

not compared with the GiCMP0 register

1 : The GiDR register is compared with the

GiCMP0 register

0 : The GiDR register (receive data register) is

not compared with the GiCMP1 register

1 : The GiDR register is compared with the

GiCMP1 register

0 : The GiDR register (receive data register) is

not compared with the GiCMP2 register

1 : The GiDR register is compared with the

GiCMP2 register

0 : The GiDR register (receive data register) is

not compared with the GiCMP3 register

1 : The GiDR register is compared with the

GiCMP3 register(2)

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