M32CSLASH86 datasheet(306/505 Pages) RENESAS

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Page 283

22. Intelligent I/O (Waveform Generating Function)

)

(

FFFF16

fBT1

65536-m

fBT1

65536

fBT1

Base Timer

(1) Free-Running Operation

(The RST2 and RST1 bits in the G1BCR1 register are set to "002")

(2) The Base Timer is Reset by Matching the Base Timer with the G1PO0 Registe

(The RST1 bit is set to "1" and the RST2 bit is set to "0")

000016

OUTC1j pin(1)

OUTC1j pin(2)

PO1jR bit in the

IIOiIR register

PO1jR bit in the

IIOiIR register

i=0 to 4, 8 to 10; j=0 to 7

m : Setting value of the G1POj register, 000016 to FFFF16

OUTC1j pin

n+2

Base Timer

000016

fBT1

n+2-m

fBT1

n+2

fBT1

i=0 to 4, 8 to 10; j=1 to 7

m : Setting value of the G1POj register, 000016 to FFFF16

n: Setting value of the G1PO0 register, 000116 to FFFD16

The above applies to the following conditions:

• The IVL bit in the G1POCRj register is set to "0" ("L" output as default value) and

the INV bit is set to "0" (not inversed).

• The UD1 and UD0 bits are set to "002" (counter increment mode).

• m<n+2

NOTES:

1. Waveform output when the INV bit in the G1POCRj register is set to "0" (not inversed)

and the IVL bit in the G1POCRi register is set to "0" (output "L" as default value).

2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set

to "1" ("H" output as default value).

Write "0" by

program if

setting to "0"

Write "0" by program

if setting to "0"

"H"

"L"

"0"

"1"

"H"

"L"

"0"

"1"

The above applies to the following condition:

• The RST2 and RST1 bits in the G1BCR1 register are set to "002" (no base timer reset

and the UD1 and UD0 bits in the G1BCR1 register to "002" (counter increment mode).

Figure 22.16 Single-Phase Waveform Output Mode

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