M32CSLASH86 datasheet(256/505 Pages) RENESAS

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Page 233

17. Serial I/O (Special Function)

)

(

Figure 17.29 SIM Interface Operation

D0 D1

D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1

D2 D3 D4 D5 D6

D0 D1 D2 D3

D4 D5 D6

D0 D1

D2 D3 D4 D5 D6

D0 D1 D2 D3

D4 D5 D6

D0 D1

D2 D3 D4 D5 D6 D7

D2 D3 D4 D5 D6

Start

bit

Parity

bit

"0"

"1"

"0"

"1"

"0"

"1"

Set to "0" by an interrupt request acknowledgement or by program

Transfer Clock

Stop

bit

Data is written to

the UARTi register

An "L" signal is applied from the SIM

card due to a parity error

An interrupt routine

detects "H" or "L"

TxDi

"0"

"1"

Transfer Clock

Read the UiRB register

Signal Line Level(3)

TxDi

Signal Line Level(2)

NOTES:

1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit.

2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi

pin and parity error signal from the receiving end, is generated.

3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the

transmitting end and parity error signal from the TxDi pin, is generated.

4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15).

Data is transferred from the UiTB

(Note 1)

RE bit in UiC1

RI bit in UiC1

IR bit in SiRIC

TE bit in UiC1

TI bit in UiC1

TXEPT bit in

UiC0 register

IR bit in SiTIC

i=0 to 4

The above applies to the following settings :

• The PRYE bit in the UiMR register is set to "1" (parity enabled)

• The STPS bit in the UiMR register is set to "0" (1 stop bit)

• The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated

when transmission completed)

Tc = 16(m+1) / fj

fj : count source frequency of the UiBRG register (f1, f8, f2n(4))

m : setting value of the UiBRG register

Start

bit

Set to "0" by an interrupt request acknowledgement or by program

Stop

bit

TxDi outputs "L" due to

a parity error

i=0 to 4

The above applies to the following settings :

• The PRYE bit in the UiMR register is set to "1" (parity enabled)

• The STPS bit in the UiMR register is set to "0" (1 stop bit)

Tc = 16(m+1) / fj

fj : count source frequency of the UiBRG register (f1, f8, f2n(4))

m : setting value of the UiBRG register

Parity

bit

"0"

"1"

"0"

"1"

(1) Transmit Timing

(2) Receive Timing

Parity Error Signal

returned from

Receiving End

Transmit Waveform

from the

Transmitting End

"1"

An interrupt routine detects

"H" or "L"

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