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M32C/86 bảng dữ liệu(PDF) 226 Page - Renesas Technology Corp |
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M32C/86 bảng dữ liệu(HTML) 226 Page - Renesas Technology Corp |
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226 / 505 page ![]() Page 203 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 17. Serial I/O (UART) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M D0 Start bit Verify if an "L" signal is applied Capture a received data UiBRG register setting output RE bit in UiC1 register RxDi Transfer Clock RI bit in UiC1 register RTSi Stop bit "1" "0" "0" "1" "H" "L" IR bit in SiRIC register "0" "1" Data is transferred from the UARTi receive register to the UiRB register Start receiving when the transfer clock is generated on the falling edge of the start bit D7 D1 Set to "0" by an interrupt request acknowledgement or by program Change to "L" by reading the UiRB register 8-bit Data Receive Timing (with no parity and 1 stop bit) i=0 to 4 NOTES: 1. The above applies when the PRYE bit in the UiMR register is set to "0" (parity disabled), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the CRS bit in the UiC0 register is set to "1" (RTS function selected). Figure 17.15 Receive Operation 17.2.1 Bit Rate In UART mode, bit rate is clock frequency which is divided by a setting value of the UiBRG (i=0 to 4) register and again divided by 16. Table 17.11 lists an example of bit rate setting. Table 17.11 Bit Rate e t a R t i B ) s p b ( t n u o C e c r u o S f o G R B i U : k c o l C n o i t c n u F l a r e h p i r e P z H M 6 1 : k c o l C n o i t c n u F l a r e h p i r e P z H M 4 2 : k c o l C n o i t c n u F l a r e h p i r e P z H M 2 3 e u l a V g n i t t e S : G R B i U f o n e t a R t i B l a u t c A ) s p b ( e u l a V g n i t t e S : G R B i U f o n e t a R t i B l a u t c A ) s p b ( e u l a V g n i t t e S : G R B i U f o n e t a R t i B l a u t c A ) s p b ( 0 0 2 18 f) h 7 6 ( 3 0 12 0 2 1) h 6 9 ( 5 5 12 0 2 1) h F C ( 7 0 22 0 2 1 0 0 4 28 f) h 3 3 ( 1 54 0 4 2) h 6 4 ( 7 74 0 4 2) h 7 6 ( 3 0 14 0 4 2 0 0 8 48 f) h 9 1 ( 5 28 0 8 4) h 6 2 ( 8 38 0 8 4) h 3 3 ( 1 58 0 8 4 0 0 6 91 f) h 7 6 ( 3 0 15 1 6 9) h 6 9 ( 5 5 15 1 6 9) h F C ( 7 0 25 1 6 9 0 0 4 4 11 f) h 4 4 ( 8 63 9 4 4 1) h 7 6 ( 3 0 13 2 4 4 1) h A 8 ( 8 3 18 8 3 4 1 0 0 2 9 11 f) h 3 3 ( 1 51 3 2 9 1) h 6 4 ( 7 71 3 2 9 1) h 7 6 ( 3 0 11 3 2 9 1 0 0 8 8 21 f) h 2 2 ( 4 31 7 5 8 2) h 3 3 ( 1 56 4 8 8 2) h 4 4 ( 8 66 8 9 8 2 0 5 2 1 31 f) h F 1 ( 1 30 5 2 1 3) h F 2 ( 7 40 5 2 1 3) h F 3 ( 3 60 5 2 1 3 0 0 4 8 31 f) h 9 1 ( 5 22 6 4 8 3) h 6 2 ( 8 32 6 4 8 3) h 3 3 ( 1 52 6 4 8 3 0 0 2 1 51 f) h 3 1 ( 9 10 0 0 0 5) h C 1 ( 8 24 2 7 1 5) h 6 2 ( 8 32 8 2 1 5 |
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