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M32C/86 bảng dữ liệu(PDF) 179 Page - Renesas Technology Corp |
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M32C/86 bảng dữ liệu(HTML) 179 Page - Renesas Technology Corp |
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179 / 505 page ![]() Page 156 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 15. Timer (Timer A) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Function (When not processing two-phase pulse signal) Function (When processing two-phase pulse signal) Timer Ai Mode Register (i=0 to 4) (Event Counter Mode) Bit Name Bit Symbol Symbol Address After Reset TA0MR to TA4MR 035616, 035716, 035816, 035916, 035A16 0016 RW 0 1 : Event counter mode(1) b1b0 Operating Mode Select Bit Count Polarity Select Bit(2) Increment/Decrement Switching Source Select Bit Count Operation Type Select Bit 0 : Normal processing operation 1 : Multiply-by-4 processing operation 0 : Reloading 1 : Free running Set to "0" in event counter mode 0 : Counts falling edges of an external signal 1 : Counts rising edges of an external signal 0 : UDF registser setting 1 : Input signal to TAiOUT pin(3) Set to "0" Set to "1" Set to "0" TMOD0 TMOD1 (b2) MR1 MR2 MR3 TCK1 TCK0 RW RW RW RW RW RW RW RW Two-Phase Pulse Signal Processing Operation Select Bit(4,5) Reserved Bit Set to "0" b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. The TAiTGH and TAiTGL bits in the ONSF or TRGSR register determine the count source in the event counter mode. 2. MR1 bit setting is enabled only when counting how many times external signals are applied. 3. The timer decrements a counter value when an "L" signal is applied to the TAiOUT pin and the timer increments a counter value when an "H" signal is applied to the TAiOUT pin. 4. The TCK1 bit is enabled only in the TA3MR register. 5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j=2 to 4) to "1" (two-phase pulse signal processing function enabled). Also, set the TAiTGH and TAiTGL bits to "002" (input to the TAjIN pin). 0 01 0 Figure 15.9 TA0MR to TA4MR Registers |
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