M32CSLASH86 datasheet(141/505 Pages) RENESAS

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Page 118

11. Interrupts

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The CANjk (j=0 to 1, k=0 to 2) interrupt and CAN1 wake-up interrupt are provided as the CAN

interrupt. The following registers are required for the CAN interrupts:

• Bits 7 in the IIO9IR to IIO11IR registers and Bits 7 in the IIO9IE to IIO11IE registers for the CAN00 to

CAN02 interrupts.

• Bits 7 in the IIO0IR, IIO1IR and IIO5IR registers and Bits 7 in the IIO0IE, IIO1IE and IIO5IE registers for

the CAN10 to CAN12 interrupts.

• Bit 6 in the IIO5IR register and Bit 6 in the IIO5IE register for the CAN1 wake-up interrupt.

The CAN0IC, CAN1IC, CAN3IC and CAN4IC registers share addresses with the following registers:

• The CAN0IC register shares an address with the IIO9IC register.

• The CAN1IC register shares an address with the IIO10IC register.

• The CAN3IC register shares an address with the IIO0IC register.

• The CAN4IC register shares an address with the IIO1IC register.

Refer to 23.4 CAN Interrupt for details.

When using the intelligent I/O interrupt or CAN interrupt to activate DMAC II, set the IRLT bit in the IIOiIE

requires.

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