M32CSLASH86 datasheet(134/505 Pages) RENESAS

134 / 505 page

Page 111

11. Interrupts

)

(

11.6.6 Saving a Register

In the interrupt sequence, the FLG register and PC are saved to the stack.

After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32

bits, are saved to the stack. Figure 11.7 shows stack states before and after an interrupt request is

acknowledged.

Other important registers are saved by program at the beginning of an interrupt routine. The PUSHM

instruction can save several registers(1) in the register bank used.

Refer to 11.4 High-Speed Interrupt for the high-speed interrupt.

NOTES:

1. Can be selected from the R0, R1, R2, R3, A0, A1, SB and FB registers.

[SP]

SP value before

an interrupt is

generated

Stack state before an interrupt request is acknowledged

Address

Stack state after an interrupt request is acknowledged

m-6

m-5

m–4

m–3

m–2

m–1

m+1

LSB

MSB

LSB

MSB

Address

The Stack

FLGL

PCH

FLGH

Content of

previous stack

Content of

previous stack

Content of

previous stack

Content of

previous stack

PCL

PCM

[SP]

New SP value

m-6

m-5

m–4

m–3

m–2

m–1

m+1

0016

Figure 11.7 Stack States

11.6.7 Restoration from Interrupt Routine

When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC before the

interrupt sequence is performed, which have been saved to the stack, are automatically restored. The pro-

gram, executed before an interrupt request was acknowledged, starts running again. Refer to 11.4 High-

Speed Interrupt for the high-speed interrupt.

Restore registers saved by program in an interrupt routine by the POPM instruction or others before the

REIT and FREIT instructions. Register bank is switched back to the bank used prior to the interrupt

sequence by the REIT or FREIT instruction.

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