H8SXSLASH1663M datasheet(838/1504 Pages) RENESAS

tên linh kiện	H8SX/1663M

Giải thích chi tiết về linh kiện	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 15 Programmable Pulse Generator (PPG)

Rev. 2.00 Sep. 24, 2008 Page 806 of 1468

REJ09B0412-0200

1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are

output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA,

and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to

enable the TGIA interrupt.

2. Write H'FF to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to

select compare match in the TPU channel set up in the previous step to be the output trigger.

Set bits G3NOV and G2NOV in PMR to 1 to select non-overlapping pulse output.

Write output data H'95 to NDRH.

3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,

outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0

to 1 (the change from 0 to 1 is delayed by the value set in TGRA).

The TGIA interrupt handling routine writes the next output data (H'65) to NDRH.

4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing

H'59, H'56, H'95... at successive TGIA interrupts.

If the DTC or DMAC is set for activation by a TGIA interrupt, pulse can be output without

imposing a load on the CPU.

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