H8SXSLASH1663M datasheet(84/1504 Pages) RENESAS

tên linh kiện	H8SX/1663M

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Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 52 of 1468

REJ09B0412-0200

2.7.1

Instructions and Addressing Modes

Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can

use.

Table 2.2

Combinations of Instructions and Addressing Modes (1)

Addressing Mode

Classifi-

cation

Instruction

Size

#xx

@ERn @(d,ERn)

@(d,

RnL.B/

Rn.W/

ERn.L)

−ERn/

@ERn

−/

+ERn @aa:8

@aa:16/

@aa:32

—

B/W/L

MOV

S/D

MOVFPE,

MOVTPE

S/D

S/D*

POP, PUSH

W/L

S/D

S/D*

LDM, STM

S/D

S/D*

Data

transfer

MOVA*

B/W

EEPMOV

SD*

MOVMD

B/W/L

SD*

Block

transfer

MOVSD

SD*

ADD, CMP

W/L

SUB

W/L

B/W/L

ADDX, SUBX

B/W/L

SD*

INC, DEC

B/W/L

ADDS, SUBS L

DAA, DAS

MULXU,

DIVXU

B/W

S:4

Arithmetic

operations

MULU, DIVU W/L

S:4

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