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H8SX1663 bảng dữ liệu(PDF) 322 Page - Renesas Technology Corp

tên linh kiện H8SX1663
Giải thích chi tiết về linh kiện  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 270 of 1102
REJ09B0294-0100
(1) Fast-Page Mode Operation Timing
When access cycles to the SDRAM space are continued and the row addresses of the consecutive
two cycles are the same, a column address output cycle follows. The row address bits to be
compared are decided by bits MXC1 and MXC0 in DRAMCR.
A fast-page mode access is performed when the access data size exceeds the bus width of the
SDRAM and when consecutive accesses to the SDRAM are generated.
Figures 6.72 and 6.73 show longword access timing of the 16-bit bus SDRAM and word access
timing of the 8-bit bus SDRAM, respectively.
T
p
T
r
T
c1
T
c2
T
c1
T
c2
CS
Precharge-sel
RAS
CAS
WE
CKE
PALL
ACTV
WRIT
NOP
NOP
DQMLU
DQMLL
BS
RD/
WR
WRIT
Address bus
Row address
Column address 1
Column address 2
SD
φ
D7 to D0
D15 to D8
Row
address
High
Figure 6.72 Longword Write Timing in 16-Bit Access Space (BE = 1, RCDM = 0)



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