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H8SX1663 bảng dữ liệu(PDF) 96 Page - Renesas Technology Corp |
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H8SX1663 bảng dữ liệu(HTML) 96 Page - Renesas Technology Corp |
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96 / 1158 page ![]() Section 2 CPU Rev.1.00 Jun. 07, 2006 Page 44 of 1102 REJ09B0294-0100 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register VBR Vector base register SBR Short address base register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition − Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR → Move ∼ Logical not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). |
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