H8SX1663 datasheet(467/1158 Pages) RENESAS

tên linh kiện	H8SX1663

Giải thích chi tiết về linh kiện	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 415 of 1102

REJ09B0294-0100

SAR

Transfer source data area

DAR

Transfer

Transfer destination data area

Figure 8.7 Memory Map in Normal Transfer Mode

8.5.5

Repeat Transfer Mode

In repeat transfer mode, one operation transfers one byte, one word, or one longword of data. By

the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to

256 transfers can be specified. When the specified number of transfers ends, the transfer counter

and address register specified as the repeat area is restored to the initial state, and transfer is

repeated. The other address register is then incremented, decremented, or left fixed. In repeat

transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when

CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU

interrupt cannot be requested when DISEL = 0.

Table 8.7 lists the register function in repeat transfer mode. Figure 8.8 shows the memory map in

repeat transfer mode.

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