H8SX1663 datasheet(423/1158 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 371 of 1102

REJ09B0294-0100

7.5.10

Bus Cycles in Dual Address Mode

(1) Normal Transfer Mode (Cycle Stealing Mode)

In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one

word, or one longword) is completed. One bus cycle or more by the CPU or DTC are executed in

the bus released cycles.

In figure 7.24, the

TEND signal output is enabled and data is transferred in words from the

external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer

mode by cycle stealing.

DMA read

cycle

DMA write

cycle

Address bus

DMA read

cycle

DMA write

cycle

DMA read

cycle

DMA write

cycle

LHWR, LLWR

TEND

Bus

released

Bus

released

Bus

released

Bus

released

Last transfer cycle

Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing

In figures 7.25 and 7.26, the

TEND signal output is enabled and data is transferred in longwords

from the external 16-bit 2-state access space to the 16-bit 2-state access space in normal transfer

mode by cycle stealing.

In figure 7.25, the transfer source (DSAR) is not aligned with a longword boundary and the

transfer destination (DDAR) is aligned with a longword boundary.

In figure 7.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer

destination (DDAR) is not aligned with a longword boundary.

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