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H8SX1663 bảng dữ liệu(PDF) 422 Page - Renesas Technology Corp

tên linh kiện H8SX1663
Giải thích chi tiết về linh kiện  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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Section 7 DMA Controller (DMAC)
Rev.1.00 Jun. 07, 2006 Page 370 of 1102
REJ09B0294-0100
7.5.9
DMA Basic Bus Cycle
Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is
transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When
the bus mastership is passed from the DMAC to the CPU, data is read from the source address and
it is written to the destination address. The bus is not released between the read and write cycles
by other bus requests. DMAC bus cycles follows the bus controller settings.
CPU cycle
DMAC cycle (one word transfer)
CPU cycle
Address bus
B
φ
T
1
T
2
T
1
T
2
T
3
T
1
T
2
T
3
Source address
Destination address
RD
LHWR
LLWR
High
Figure 7.23 Example of Bus Timing of DMA Transfer



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