HD6432351 datasheet(322/1025 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 288 of 988

REJ09B0330-0300

Figure 7.42 shows an example in which a low level is not output at the

TEND pin.

Internal address

Internal read signal

External address

HWR, LWR

Internal write signal

TEND

Not output

DMA

read

External write by CPU, etc.

DMA

write

Figure 7.42 Example in Which Low Level Is Not Output at

TEND

TEND Pin

Activation by Falling Edge on

DREQ

DREQ Pin

DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.

The operation is as follows:

[1] Activation request wait state: Waits for detection of a low level on the

DREQ pin, and

switches to [2].

[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].

[3] Activation request disabled state: Waits for detection of a high level on the

DREQ pin, and

switches to [1].

After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is

enabled is performed by detection of a low level.

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