HD6432351 datasheet(155/1025 Pages) RENESAS

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Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 121 of 988

REJ09B0330-0300

Section 6 Bus Controller

6.1

Overview

The H8S/2350 Group has a built-in bus controller (BSC) that manages the external address space

divided into eight areas. The bus specifications, such as bus width and number of access states,

can be set independently for each area, enabling multiple memories to be connected easily.

The bus controller also has a bus arbitration function, and controls the operation of the internal bus

masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC).

6.1.1

Features

The features of the bus controller are listed below.

• Manages external address space in area units

 In advanced mode, manages the external space as 8 areas of 2-Mbytes

 In normal mode, manages the external space as a single area

 Bus specifications can be set independently for each area

 DRAM/burst ROM interfaces can be set

• Basic bus interface

 Chip select (CS0 to CS7) can be output for areas 0 to 7

 8-bit access or 16-bit access can be selected for each area

 2-state access or 3-state access can be selected for each area

 Program wait states can be inserted for each area

• DRAM interface

 DRAM interface can be set for areas 2 to 5 (in advanced mode)

 Row address/column address multiplexed output (8/9/10 bits)

 Two byte access methods (2-CAS)

 Burst operation (fast page mode)

 TP cycle insertion to secure RAS precharging time

 Choice of CAS-before-RAS refreshing or self-refreshing

• Burst ROM interface

 Burst ROM interface can be set for area 0

 Choice of 1- or 2-state burst access

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