HD6432351 datasheet(150/1025 Pages) RENESAS

tên linh kiện	HD6432351

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Section 5 Interrupt Controller

Rev. 3.00 Sep 15, 2006 page 116 of 988

REJ09B0330-0300

Internal

address bus

Internal

write signal

TGIEA

TGFA

TGI0A

interrupt signal

TIER0 write cycle by CPU

TGI0A exception handling

TIER0 address

Figure 5.8 Contention between Interrupt Generation and Disabling

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while

the interrupt is masked.

5.5.2

Instructions That Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these

instructions is executed, all interrupts including NMI are disabled and the next instruction is

always executed. When the I bit is set by one of these instructions, the new value becomes valid

two states after execution of the instruction ends.

5.5.3

Times when Interrupts Are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.

The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has

updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

HD6432351 bảng dữ liệu(PDF) 150 Page - Renesas Technology Corp