HD6432351 datasheet(726/1025 Pages) RENESAS

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Section 20 Power-Down Modes

Rev. 3.00 Sep 15, 2006 page 692 of 988

REJ09B0330-0300

20.5

Module Stop Mode

20.5.1

Module Stop Mode

Module stop mode can be set for individual on-chip supporting modules.

When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of

the bus cycle and a transition is made to module stop mode. The CPU continues operating

independently.

Table 20.3 shows MSTP bits and the corresponding on-chip supporting modules.

When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module

starts operating at the end of the bus cycle. In module stop mode, the internal states of modules

other than the SCI and A/D converter are retained.

After reset clearance, all modules other than DMAC and DTC are in module stop mode.

When an on-chip supporting module is in module stop mode, read/write access to its registers is

disabled.

Do not make a transition to sleep mode with MSTPCR set to H'FFFF, as this will halt operation of

the bus controller.

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