HD6432351 datasheet(725/1025 Pages) RENESAS

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Section 20 Power-Down Modes

Rev. 3.00 Sep 15, 2006 page 691 of 988

REJ09B0330-0300

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made

to software standby mode. When software standby mode is cleared by an external interrupt,

medium-speed mode is restored.

When the

RES pin is driven low, a transition is made to the reset state, and medium-speed mode is

cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.

When the

STBY pin is driven low, a transition is made to hardware standby mode.

Figure 20.1 shows the timing for transition to and clearance of medium-speed mode.

φ,

Bus master clock

supporting module clock

Internal address bus

Internal write signal

Medium-speed mode

SCKCR

Figure 20.1 Medium-Speed Mode Transition and Clearance Timing

20.4

Sleep Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters

sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers

are retained. Other supporting modules do not stop.

Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program

execution state via the exception handling state. Sleep mode is not cleared if interrupts are

disabled, or if interrupts other than NMI are masked by the CPU.

When the

STBY pin is driven low, a transition is made to hardware standby mode.

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