HD6432351 datasheet(484/1025 Pages) RENESAS

484 / 1025 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 450 of 988

REJ09B0330-0300

10.2.9

Timer Synchro Register (TSYR)

—

SYNC5

R/W

SYNC4

R/W

SYNC3

R/W

SYNC0

R/W

SYNC2

R/W

SYNC1

R/W

Bit

Initial value

R/W

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous

operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when

the corresponding bit in TSYR is set to 1.

TSYR is initialized to H'00 by a reset, and in hardware standby mode.

Bits 7 and 6—Reserved: Should always be written with 0.

Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is

independent of or synchronized with other channels.

When synchronous operation is selected, synchronous presetting of multiple channels*1, and

synchronous clearing through counter clearing on another channel*2 are possible.

Bit n

SYNCn

Description

TCNTn operates independently (TCNT presetting/clearing is unrelated to

other channels)

(Initial value)

TCNTn performs synchronous operation

TCNT synchronous presetting/synchronous clearing is possible

Notes: n = 5 to 0

1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.

2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source

must also be set by means of bits CCLR2 to CCLR0 in TCR.

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