HD6432351 datasheet(483/1025 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 449 of 988

REJ09B0330-0300

10.2.8

Timer Start Register (TSTR)

—

CST5

R/W

CST4

R/W

CST3

R/W

CST0

R/W

CST2

R/W

CST1

R/W

Bit

Initial value

R/W

TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.

TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating

mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.

Bits 7 and 6—Reserved: Should always be written with 0.

Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for

TCNT.

Bit n

CSTn

Description

TCNTn count operation is stopped

(Initial value)

TCNTn performs count operation

Notes: 1. n = 5 to 0

2. If 0 is written to the CST bit during operation with the TIOC pin designated for output,

the counter stops but the TIOC pin output compare output level is retained. If TIOR is

written to when the CST bit is cleared to 0, the pin output level will be changed to the

set initial output value.

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