HD6432351 datasheet(355/1025 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev. 3.00 Sep 15, 2006 page 321 of 988

REJ09B0330-0300

8.5

Usage Notes

Module Stop

When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the

module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating.

On-Chip RAM

The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the

DTC is used, the RAME bit in SYSCR must not be cleared to 0.

DMAC Transfer End Interrupt

When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer

counter and DISEL bit, the DMAC’s DTE bit is not subject to DTC control, and the write data has

priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer

counter reaches 0.

DTCE Bit Setting

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts

are masked, multiple activation sources can be set at one time by writing data after executing a

dummy read on the relevant register.

HD6432351 bảng dữ liệu(PDF) 355 Page - Renesas Technology Corp