HD6432351 datasheet(353/1025 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev. 3.00 Sep 15, 2006 page 319 of 988

REJ09B0330-0300

chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH

address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.

[2] Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing

(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0

= 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in

DAR, and the data table size in CRA. CRB can be set to any value.

[3] Locate the TPU transfer register information consecutively after the NDR transfer register

information.

[4] Set the start address of the NDR transfer register information to the DTC vector address.

[5] Set the bit corresponding to TGIA in DTCER to 1.

[6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA

interrupt with TIER.

[7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and

NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to

be used as the output trigger.

[8] Set the CST bit in TSTR to 1, and start the TCNT count operation.

[9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and the

set value of the next output trigger period is transferred to TGRA. The activation source TGFA

flag is cleared.

[10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the

TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the

CPU. Termination processing should be performed in the interrupt handling routine.

(3) Software Activation

An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means

of software activation. The transfer source address is H'1000 and the destination address is

H'2000. The vector number is H'60, so the vector address is H'04C0.

[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination

address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =

0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =

0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,

and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.

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