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H838532H bảng dữ liệu(PDF) 299 Page - Renesas Technology Corp |
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H838532H bảng dữ liệu(HTML) 299 Page - Renesas Technology Corp |
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299 / 508 page ![]() Section 9 Timers Rev. 1.00 May 30, 2008 Page 279 of 484 REJ09B0436-0100 (3) Event Counter L (ECL) ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The event clock from the external asynchronous event AEVL pin is used as the input clock source. ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset. ECL7 ECL2 ECL1 ECL0 ECL6 ECL5 ECL4 ECL3 76543210 0 000 00 00 R RRR RRR R Bit Initial Value Read/Write (4) Clock Stop Register 2 (CKSTPR2) — WDCKSTP PWCKSTP LDCKSTP — — — AECKSTP 7 6 543210 1 1111111 — R/W R/W R/W ——— R/W Bit Initial value Read/Write CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the asynchronous event counter is described here. For details of the other bits, see the sections on the relevant modules. Bit 3: Asynchronous event counter module standby mode control (AECKSTP) Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter. AECKSTP Description 0 Asynchronous event counter is set to module standby mode 1 Asynchronous event counter module standby mode is cleared (initial value) |
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