H838532H datasheet(296/508 Pages) RENESAS

296 / 508 page

Section 9 Timers

Rev. 1.00 May 30, 2008 Page 276 of 484

REJ09B0436-0100

Bit 7: Counter overflow flag H (OVH)

Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when

ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by reading

it when set to 1, then writing 0.

When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a

status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.

Bit 7

OVH

Description

ECH has not overflowed

(initial value)

Clearing condition:

After reading OVH = 1, cleared by writing 0 to OVH

ECH has overflowed

Setting condition:

Set when ECH overflows from H’FF to H’00

Bit 6: Counter overflow flag L (OVL)

Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when

ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by reading

it when set to 1, then writing 0.

Bit 6

OVL

Description

ECL has not overflowed

(initial value)

Clearing condition:

After reading OVL = 1, cleared by writing 0 to OVL

ECL has overflowed

Setting condition:

Set when ECL overflows from H'FF to H'00 while CH2 is set to 1

Bit 5: Reserved bit

Bit 5 is reserved; it can be read and written, and is initialized to 0 upon reset.

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