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H838532H bảng dữ liệu(PDF) 162 Page - Renesas Technology Corp

tên linh kiện H838532H
Giải thích chi tiết về linh kiện  16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series
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Section 6 ROM
Rev. 1.00 May 30, 2008 Page 142 of 484
REJ09B0436-0100
6.6
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
6.6.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode,
or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), and erase block register (EBR) are initialized. In a reset via the
RES pin, the reset
state is not entered unless the
RES pin is held low until oscillation stabilizes after powering on. In
the case of a reset during operation, hold the
RES pin low for the RES pulse width specified in the
AC Characteristics section.
6.6.2
Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block
register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00, erase
protection is set for all blocks.
6.6.3
Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing



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