H838532H datasheet(128/508 Pages) RENESAS

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Section 5 Power-Down Modes

Rev. 1.00 May 30, 2008 Page 108 of 484

REJ09B0436-0100

SLEEP instruction fetch

Internal data bus

Fetch of next instruction

Port output

Pins

High-impedance

Active (high-speed) mode or active (medium-speed) mode

Standby mode

SLEEP instruction execution

Internal processing

Figure 5.2 Standby Mode Transition and Pin States

5.3.5

Notes on External Input Signal Changes before/after Standby Mode

1. When external input signal changes before/after standby mode or watch mode

When an external input signal such as

IRQ or WKP is input, both the high- and low-level

widths of the signal must be at least two cycles of system clock

φ or subclock φSUB (referred

to together in this section as the internal clock). As the internal clock stops in standby mode

and watch mode, the width of external input signals requires careful attention when a transition

is made via these operating modes. Ensure that external input signals conform to the conditions

stated in 3, Recommended timing of external input signals, below.

2. When external input signals cannot be captured because internal clock stops

The case of falling edge capture is illustrated in figure 5.3

As shown in the case marked "Capture not possible," when an external input signal falls

immediately after a transition to active (high-speed or medium-speed) mode or subactive

mode, after oscillation is started by an interrupt via a different signal, the external input signal

cannot be captured if the high-level width at that point is less than 2 t

cyc or 2 tsubcyc.

3. Recommended timing of external input signals

To ensure dependable capture of an external input signal, high- and low-level signal widths of

at least 2 t

cyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch

mode, as shown in "Capture possible: case 1."

External input signal capture is also possible with the timing shown in "Capture possible: case

2" and "Capture possible: case 3," in which a 2 t

cyc or 2 tsubcyc level width is secured.

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