R8C2K datasheet(147/471 Pages) RENESAS

147 / 471 page

R8C/2K Group, R8C/2L Group

15. Watchdog Timer

Rev.1.10

Dec 21, 2007

Page 130 of 450

REJ09B0406-0110

Figure 15.2

Registers WDTR, WDTS, and WDC

Watchdog Timer Control Register

Symbol

Address

After Reset

WDC

000Fh

00X11111b

Bit Symbol

Bit Name

Function

Reserved bit

Set to 0. When read, the content is undefined.

WDC7

—

(b6)

Reserved bit

Set to 0.

Prescaler select bit

0 : Divide-by-16

1 : Divide-by-128

b7 b6 b5 b4

High-order bits of w atchdog timer

—

(b4-b0)

—

(b5)

b3 b2 b1 b0

Watchdog Timer Reset Register

Symbol

Address

After Reset

WDTR

000Dh

Undefined

NOTES:

When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)

The default value of the w atchdog timer is 7FFFh w hen count source protection

mode is disabled and 0FFFh w hen count source protection mode is enabled.(2)

Function

Do not generate an interrupt betw een w hen 00h and FFh are w ritten.

When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),

0FFFh is set in the w atchdog timer.

Watchdog Timer Start Register

Symbol

Address

After Reset

WDTS

000Eh

Undefined

Function

The w atchdog timer starts counting after a w rite instruction to this register.

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