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R8C bảng dữ liệu(PDF) 120 Page - Renesas Technology Corp

tên linh kiện R8C
Giải thích chi tiết về linh kiện  RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  199 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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R8C bảng dữ liệu(HTML) 120 Page - Renesas Technology Corp

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R8C/10 Group
Rev.1.20 Jan 27, 2006
page 110 of 180
REJ09B0019-0120
14.3 Sample and Hold
If the SMP bit in the ADCON2 register is set to “1” (with sample-and-hold), the conversion speed per
pin is increased to 28 ØAD cycles for 8-bit resolution or 33 ØAD cycles for 10-bit resolution. Sample-
and-hold is effective in all operation modes. Select whether or not to use the sample-and-hold function
before starting A/D conversion.
When performing the A/D conversion, charge the comparator capacitor inside the microcomputer.
Figure 14.6 shows the A/D conversion timing diagram.
14.3 Sample & Hold/14.4 A/D conversion cycles
Figure 14.6 A/D Conversion Timing Diagram
Sampling time
4
φ AD cycle
Comparison
time
Sampling time
2.5
φ AD cycle
Comparison
time
Sampling time
2.5
φ AD cycle
Comparison
time
* Repeat until conversion ends
Conversion time at the 1st bit
at the 2nd bit
Sample & Hold
disabled
Sample & Hold
enabled
Conversion time at the 1st bit
at the 2nd bit
Sampling time
4
φ AD cycle
Comparison
time
Comparison
time
Comparison
time
* Repeat until conversion ends
* Repeat until conversion ends
14.4 A/D conversion cycles
Figure 14.7 shows the A/D conversion cycles.
Figure 14.7 A/D Conversion Cycles
A/D conversion mode
Without sample & hold
Without sample & hold
With sample & hold
With sample & hold
8 bits
10 bits
8 bits
10 bits
Conversion
time
Comparison
time
Comparison
time
End process
Sampling
time
Sampling
time
49
φ AD
59
φ AD
28
φ AD
33
φ AD
2.0
φ AD
2.0
φ AD
2.5
φ AD
2.5
φ AD
2.5
φ AD
2.5
φ AD
2.5
φ AD
2.5
φ AD
8.0
φ AD
8.0
φ AD
4.0
φ AD
4.0
φ AD
4
φ AD
4
φ AD
4
φ AD
4
φ AD
2.5
φ AD
2.5
φ AD
0.0
φ AD
0.0
φ AD
End process
Conversion time at the
2nd bit and the follows
Conversion time
at the 1st bit



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