M66596FP datasheet(128/131 Pages) RENESAS

128 / 131 page

REVISION HISTORY

M66596 Data Sheet

Description

Rev.

Date

Page

Summary

0.79

2004.07.7

First edition issued

0.79A

2004.07.21

52-53

Change *3), *5), *6) of Table 1.1

Change INDEX of Table 3.1

Change INDEX of Table 3.2

Change note *2) --> *1) of Table 3.2

Delete note *3) of Table 3.2

(1.3)

Added:

Figure 1.2

(1.4)

Modified:

“Table 1.1 describes the controller pins.”

(1.6)

Modified:

“The controller is configured with an analog front end unit (AFE),”

(2.1)

Corrected:

Addr 0x6C “Pipe period control register”

13-14

(2.2)

Added:

Addr 0x32 “BRDYM”, “PCSE”

Addr 0x70 – 0x78 “INBUFM”

15-45

(2.3-2.14)

Added and corrected : Refernce to chaptor 2 and 3 in noteof table.

Corrected: Note *1)

(2.3)

Added: “or clock stop state”

Corrected: Note *1)

(2.4.1)

Modified: “Each bit of the DVSTCTR register”

Added: “According to the USB specification, USB idle state…”

(2.5)

Modified: Note *1)

(2.5.2)

Modified: “Table 2.7 and Table 2.8 show the byte Endian operation…”

25(2.6)

Corrected: Note 5, 6, 7, 8

Corrected: Note *7)

(2.7)

Added: PCSE and BRDYM bits

Added: Note *3), *4)

(2.13)

Corrected: PID bit

Modified: Note *5)

42-45

(2.14)

Corrected: Note *4), *5), *6), *7)

Corrected: Default value of bit6 of PIPEMAXP

Corrected and added: Note *12), *13), *14), *15)

104

(4)

Moved: Chaptor3 to Chaptor4

105,106

(4.3,4.4)

Corrected:

Average supply current at HS operation; 60mA to 40mA.

0.80

2004.10.5

(3)

Added: Chaptor 3 Description of Operation

(1.7)

Added: 1.7

1.00

2006.3.14

(2.2)

Corrected: Addr 0x68, 0x6A

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