M37270MF datasheet(19/95 Pages) RENESAS

19 / 95 page

MITSUBISHI MICROCOMPUTERS

M37270MF-XXXSP

M37270EF-XXXSP, M37270EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

Fig. 11. Structure of serial I/O mode register

Internal clock—the serial I/O counter is set to “7” during write cycle

into the serial I/O register (address 021416), and transfer clock goes

“H” forcibly. At each falling edge of the transfer clock after the write

cycle, serial data is output from the SOUT pin. Transfer direction can

be selected by bit 5 of the serial I/O mode register. At each rising

edge of the transfer clock, data is input from the SIN pin and data in

the serial I/O register is shifted 1 bit.

After the transfer clock has counted 8 times, the serial I/O counter

becomes “0” and the transfer clock stops at “H.” At this time the inter-

rupt request bit is set to “1.”

External clock—when an external clock is selected as the clock

source, the interrupt request is set to “1” after the transfer clock has

counted 8 times. However, transfer operation does not stop, so con-

trol the clock externally. Use the external clock of 500kHz or less

with a duty cycle of 50%.

The serial I/O timing is shown in Figure 10. When using an external

clock for transfer, the external clock must be held at “H” for initializing

the serial I/O counter. When switching between an internal clock and

an external clock, do not switch during transfer. Also, be sure to ini-

tialize the serial I/O counter after switching.

Notes 1: On programming, note that the serial I/O counter is set by

writing to the serial I/O register with the bit managing in-

structions as SEB and CLB instructions.

2: When an external clock is used as the synchronizing clock,

write transmit data to the serial I/O register at “H” of the

transfer clock input level.

Fig. 10. Serial I/O timing (for LSB first)

Synchroninzing clock

Transfer clock

Serial I/O register

write signal

Serial I/O output

SOUT

(Note)

Serial I/O input

SIN

Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed.

Interrupt request bit is set to “1”

Serial I/O mode register

(SM : address 021316)

Internal synchronizing clock

selection bits

b1 b0

0 : f(XIN)/8 or f(XCIN)/8

1 : f(XIN)/16 or f(XCIN)/16

0 : f(XIN)/32 or f(XCIN)/32

1 : f(XIN)/64 or f(XCIN)/64

Synchronizing clock selection bit

0 : External clock

1 : Internal clock

Port function selection bit

0 : P11, P13 functions as port

1 : SCL1, SDA1

Port function selection bit

0 : P12, P14 functions as port

1 : SCL2, SDA2

Transfer direction selection bit

0 : LSB first

1 : MSB first

Fix these bits to “0”

M37270MF bảng dữ liệu(PDF) 19 Page - Renesas Technology Corp

M37270MF bảng dữ liệu(HTML) 19 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

bảng dữ liệu tải về

Link URL