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7540 bảng dữ liệu(PDF) 59 Page - Renesas Technology Corp |
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7540 bảng dữ liệu(HTML) 59 Page - Renesas Technology Corp |
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59 / 88 page ![]() 7540 Group Rev.4.00 Jun 21, 2004 page 59 of 82 REJ03B0011-0400Z Table 16 Timing requirements (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min.Typ.Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input “H” pulse width CNTR0, INT0, INT1, input “L” pulse width CNTR1 input cycle time CNTR1 input “H” pulse width CNTR1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2–SCLK2) th(SCLK2–SDATA2) 2 500 200 200 1000 460 460 8000 3200 3200 4000 1900 1900 800 400 4000 1900 1900 800 800 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. |
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