7480 datasheet(11/98 Pages) RENESAS

11 / 98 page

MITSUBISHI MICROCOMPUTERS

7480/7481 GROUP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

CPU Mode Register

The stack page selection bit is assigned to the CPU mode regis-

ter. This register is allocated at address 00FB16.

Fig. 7 Structure of CPU mode register

FUNCTIONAL DESCRIPTION

Central Processing Unit (CPU)

The 7480/7481 group uses the standard 740 family CPU. Refer to

the table of 740 family addressing modes and machine instruc-

tions or the MELPS 740 programming manual for details on the

instruction set.

Machine-resident 740 family instructions are as follows:

1. The FST and SLW instructions are not available.

2. The MUL and DIV instructions are available.

3. The WIT instruction is available. (Note)

4. The STP instruction is available. (Note)

Note: When using these instructions, refer to the corresponding

chapter “STP and WIT instruction control” below.

CPU mode register (CPUM: address 00FB16)

Stack page selection bit (Note)

Page 0

Page 1

System clock division proportion selection bit

f = f(XIN)/2 (high-speed mode)

f = f(XIN)/8 (medium-speed mode)

Not used.

These bits must always be set to “0”.

Watchdog timer L count source selection bit

f(XIN)/8

f(XIN)/16

Note : In the models of RAM size under 192 bytes, set this bit to “0”.

Not used (undefined at read)

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