R32C121 datasheet(85/113 Pages) RENESAS

85 / 113 page

REJ03B0237-0050 Rev.0.50 Jul 31, 2008

Page 85 of 111

Under development

Preliminary Specification

This is a preliminary specification and is subject to change.

R32C/121 Group

5. Electrical Characteristics

Timing Requirements (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted)

Figure 5.5

Flash Memory CPU Rewrite Mode Timing

Table 5.15

Flash Memory CPU Rewrite Mode Timing

Symbol

Characteristics

Value

Unit

Min.

Max.

tcR

Read cycle time

200

tsu(S-R)

Chip-select setup time for read

200

th(R-S)

Chip-select hold time after read

0ns

tsu(A-R)

Address setup time for read

200

th(R-A)

Address hold time after read

0ns

tw(R)

Read pulse width

100

tcW

Write cycle time

200

tsu(S-W)

Chip-select setup time for write

0ns

th(W-S)

Chip-select hold time after write

tsu(A-W)

Address setup time for write

0ns

th(W-A)

Address hold time after write

tw(W)

Write pulse width

CS0

A23 to A0, BC0 to BC3

t h(R-S)

Read cycle

t w(R)

t su(S-R)

t h(R-A)

t su(A-R)

Write cycle

CS0 to CS3

A23 to A0, BC0 to BC3

t h(W-S)

t w(W)

t su(S-W)

t h(W-A)

t su(A-W)

t cW

t cR

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