M38265EBFS datasheet(77/91 Pages) RENESAS

77 / 91 page

Rev.1.00

Sep 06, 2006

page 77 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

3.3.5 Notes on timer

This clause describes notes for the various operation modes of Timer X, Timer Y, Timer 1, Timer 2, and

Timer 3.

(1) Timer X

■For all modes

◆When reading and writing to the timer X high-order and low-order registers, be sure to read/write

both the timer X high- and low-order registers.

When reading the timer X high-order and low-order registers, read the high-order register first.

When writing to the timer X high-order and low-order registers, write the low-order register first.

The timer X cannot perform the correct operation if the next operation is performed.

•Write operation to the high- or low-order register before reading the timer X low-order register

•Read operation from the high- or low-order register before writing to the timer X high-order

◆When the operation “writing data only to the latch” is selected by the timer X write control bit (bit

0 of timer X mode register (address 2716)) is selected, a value is simultaneously set to the timer

X and the timer X latch if the writing in the high-order register and the underflow of timer X are

performed at the same timing. Unexpected value may be set in the high-order timer on this

occasion.

■Pulse output mode

◆When reading port P54 (bit 4 of port P5 register (address 0A16)) in the pulse output mode, the

pin state is read instead of the contents of the port latch.

■Real time port function

◆After reset is released, the port P5 direction register is set as the input mode and ports P50–P57

functions as regular ports. To use as the RTP function pin, set the corresponding bit of the port

P5 direction register to the output mode.

■CNTR0 active edge selection

◆The CNTR0 active edge selection bit (bit 6 of timer X mode register) also effects the active edge

of the generation of the CNTR0 interrupt request.

(2) Timer Y

■For all modes

◆When reading and writing to the timer Y high-order and low-order registers, be sure to read/write

both the timer Y high- and low-order registers.

When reading the timer Y high-order and low-order registers, read the high-order register first.

When writing to the timer Y high-order and low-order registers, write the low-order register first.

The timer Y cannot perform the correct operation if the next operation is performed.

•Write operation to the high- or low-order register before reading the timer Y low-order register

•Read operation from the high- or low-order register before writing to the timer Y high-order

■CNTR1 active edge selection

◆The CNTR1 active edge selection bit (bit 6 of timer Y mode register (address 2816)) also effects

the active edge of the generation of the CNTR1 interrupt request. However, both edges are valid

for the request generation regardless of the bit state in the continuous HL pulse-width measurement

mode.

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