M38265EBFS datasheet(51/91 Pages) RENESAS

51 / 91 page

Rev.1.00

Sep 06, 2006

page 51 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

TOUT/φ OUTPUT FUNCTION

The system clock φ or timer 2 divided by 2 (TOUT output) can be

output from port P43 by setting the TOUT/φ output enable bit of the

timer 123 mode register and the TOUT/φ output control register.

Set the P43/φ/TOUT pin to output mode (set “1” to bit 3 of port P4

direction register) when outputting TOUT/φ.

Fig. 55 Structure of TOUT/φ

φφ

φ output-related registers

TOUT/φ output control bit

0 : System clock φ output

1 : TOUT output

Not used (“0” at reading)

TOUT/φ output control register

(CKOUT : address 002A16)

Timer 123 mode register

(T123M : address 002916)

TOUT output active edge switch bit

0 : Start at “H” output

1 : Start at “L” output

TOUT/φ output enable bit

0 : TOUT/φ output disabled

1 : TOUT/φ output enabled

Timer 2 write control bit

0 : Write data in latch and timer

1 : Write data in latch only

Timer 2 count source selection bit

0 : Timer 1 output

1 : f(XIN)/16

(or f(XCIN)/16 in low-speed mode)

Timer 3 count source selection bit

0 : Timer 1 output

1 : f(XIN)/16

(or f(XCIN)/16 in low-speed mode)

Timer 1 count source selection bit

0 : f(XIN)/16

(or f(XCIN)/16 in low-speed mode)

1 : f(XCIN)

Not used (“0” at reading)

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