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M38263E2FS bảng dữ liệu(PDF) 58 Page - Renesas Technology Corp |
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M38263E2FS bảng dữ liệu(HTML) 58 Page - Renesas Technology Corp |
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58 / 91 page ![]() Rev.1.00 Sep 06, 2006 page 58 of 88 REJ03B0181-0100 3826 Group (One Time PROM version) NOTES ON USE Countermeasures Against Noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20 mm). ● Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is com- pletely initialized. This may cause a program runaway. Fig. 64 Wiring for clock I/O pins (2) Connection of bypass capacitor across VSS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: • Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. • Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for VSS line and VCC line. • Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Fig. 63 Wiring for the RESET pin ➁ Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS patterns. ● Reason If noise enters clock I/O pins, clock waveforms may be de- formed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscil- lator, the correct clock will not be input in the microcomputer. Fig. 65 Bypass capacitor across the VSS line and the VCC line RESET Reset circuit Noise VSS VSS Reset circuit VSS RESET VSS N.G. O.K. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. VSS VCC VSS VCC N.G. O.K. |
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