M38262EBGP datasheet(31/91 Pages) RENESAS

31 / 91 page

Rev.1.00

Sep 06, 2006

page 31 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) is selected by setting

the serial I/O1 mode selection bit of the serial I/O1 control register

to “0”.

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer regis-

ter, but the two buffers have the same address (001816) in

memory. Since the shift register cannot be written to or read from

directly, transmit data is written to the transmit buffer, and receive

data is read from the receive buffer.

The transmit buffer can also hold the next data to be transmitted

during transmitting, and the receive buffer register can hold re-

ceived one-byte data while the next one-byte data is being re-

ceived.

Fig. 28 Block diagram of UART serial I/O1

Fig. 29 Operation of UART serial I/O1 function

XIN

1/4

PE FE

1/16

Data bus

Receive buffer register

Address 001816

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request

Baud rate generator

Frequency division ratio 1/(n+1)

Address 001C16

ST/SP/PA generator

Transmit buffer register

Data bus

Transmit shift register

Address 001816

Transmit shift register shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request

Address 001916

STdetector

SP detector

UART control register

Address 001B16

Character length selection bit

Address 001A16

BRG count source selection bit

Transmit interrupt source selection bit

Serial I/O1 synchronization clock selection bit

Clock control circuit

Character length selection bit

7 bits

8 bits

Serial I/O1 control register

P46/SCLK1

Serial I/O1 status register

P44/RXD

P45/TXD

TSC = “0”

TBE = “1”

RBF = “0”

TBE = “0”

RBF = “1”

TBE = “1”TSC = “1”✽

Transmit buffer register write signal

✽ Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bits

1 or 0 parity bit

1 or 2 stop bit (s)

1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit for reception).

2 : The serial I/O1 receive interrupt request occurs when the receive buffer full flag (RBF) becomes “1”.

3 : Select the serial I/O1 transmit interrupt request occurrence factor between when the transmit buffer register has emptied (TBE = “1”) or

after the transmit shift operation has ended (TSC = “1”), by setting the transmit interrupt source selection bit (TIC) of the serial

I/O1 control register.

Notes

Serial output TxD

Serial input RxD

Receive buffer register read signal

Transmit or receive clock

(Notes 1, 2)

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