M38262EBGP datasheet(27/91 Pages) RENESAS

27 / 91 page

Rev.1.00

Sep 06, 2006

page 27 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

Timer X

Timer X is a 16-bit timer and is equipped with the timer latch. The

division ratio of timer X is given by 1/(n+1), where n is the value in

the timer latch. Timer X is a down-counter. When the contents of

timer X reach “000016”, an underflow occurs at the next count

pulse and the contents of the timer latch are reloaded into the

timer and the count is continued. When the timer underflows, the

timer X interrupt request bit is set to “1”.

Timer X can be selected in one of four modes by the timer X mode

port.

(1) Timer mode

The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).

(2) Pulse output mode

Each time the timer underflows, a signal output from the CNTR0

pin is inverted. Except for this, the operation in pulse output mode

is the same as in timer mode. When using a timer in this mode,

set the P54/CNTR0 pin to output mode (set “1” to bit 4 of port P5

direction register).

(3) Event counter mode

The timer counts signals input through the CNTR0 pin.

Except for this, the operation in event counter mode is the same

as in timer mode. When using a timer in this mode, set the P54/

CNTR0 pin to input mode (set “0” to bit 4 of port P5 direction reg-

ister).

(4) Pulse width measurement mode

The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If

CNTR0 active edge switch bit is “0”, the timer counts while the

input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts

while the input signal of CNTR0 pin is at “L”. When using a timer in

this mode, set the P54/CNTR0 pin to input mode (set “0” to bit 4 of

port P5 direction register).

●Read and write to timer X high-order, low-order registers

When reading and writing to the timer X high-order and low-order

registers, be sure to read/write both the timer X high- and low-or-

der registers.

When reading the timer X high-order and low-order registers, read

the high-order register first. When writing to the timer X high-order

and low-order registers, write the low-order register first. The timer

X cannot perform the correct operation if the next operation is per-

formed.

•Write operation to the high- or low-order register before reading

the timer X low-order register

•Read operation from the high- or low-order register before writing

to the timer X high-order register

Fig. 23 Structure of timer X mode register

Timer X mode register

(TXM : address 002716)

Timer X write control bit

0 : Write value in latch and timer

1 : Write value in latch only

Real time port control bit

0 : Real time port function invalid

1 : Real time port function valid

RTP0 data for real time port

RTP1 data for real time port

Timer X operating mode bits

b5 b4

00 : Timer mode

01 : Pulse output mode

10 : Event counter mode

11 : Pulse width measurement mode

CNTR0 active edge switch bit

0 : Count at rising edge in event counter mode

Start from “H” output in pulse output mode

Measure “H” pulse width in pulse width measurement

mode

Falling edge active for CNTR0 interrupt

1 : Count at falling edge in event counter mode

Start from “L” output in pulse output mode

Measure “L” pulse width in pulse width measurement

mode

Rising edge active for CNTR0 interrupt

Timer X stop control bit

0 : Count start

1 : Count stop

●Timer X Write Control

Which write control can be selected by the timer X write control bit

(bit 0) of the timer X mode register (address 002716), writing data

to both the latch and the timer at the same time or writing data

only to the latch. When the operation “writing data only to the

latch” is selected, the value is set to the timer latch by writing data

to the timer X register and the timer is updated at next underflow.

After reset, the operation “writing data to both the latch and the

timer at the same time” is selected, and the value is set to both

the latch and the timer at the same time by writing data to the

timer X register. The write operation is independent of timer X

count operation, operating or stopping.

When the value is written in latch only, a value is simultaneously

set to the timer X and the timer X latch if the writing in the high-

order register and the underflow of timer X are performed at the

same timing. Unexpected value may be set in the high-order timer

on this occasion.

●Real Time Port Control

While the real time port function is valid, data for the real time port

are output from ports P52 and P53 each time the timer X

underflows. (However, if the real time port control bit is changed

from “0” to “1” after set of the real time port data, data are output

independent of the timer X operation.) If the data for the real time

port is changed while the real time port function is valid, the

changed data are output at the next underflow of timer X.

Before using this function, set the P52/RTP0, P53/RTP1 pins to

output mode (set “1” to bits 2, 3 of port P5 direction register).

■Note on CNTR0 interrupt active edge selection

CNTR0 interrupt active edge depends on the CNTR0 active edge

switch bit.

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