SN75DP118

PIN FUNCTIONS

PIN

I/O

DESCRIPTION

SIGNAL

NO.

MAIN LINK INPUT PINS

ML_IN 0

34, 35

I

DisplayPort Main Link Channel 0 Differential Input

ML_IN 1

2, 3

I

DisplayPort Main Link Channel 1 Differential Input

ML_IN 2

5, 6

I

DisplayPort Main Link Channel 2 Differential Input

ML_IN 3

8, 9

I

DisplayPort Main Link Channel 3 Differential Input

MAIN LINK OUTPUT PINS

ML_OUT 0

30, 29

O

DisplayPort Main Link Port A Channel 0 Differential Output

ML_OUT 1

26, 25

O

DisplayPort Main Link Port A Channel 1 Differential Output

ML_OUT 2

23, 22

O

DisplayPort Main Link Port A Channel 2 Differential Output

ML_OUT 3

20, 19

O

DisplayPort Main Link Port A Channel 3 Differential Output

HOT PLUG DETECT PINS0

HPD_OUT

11

O

Hot Plug Detect Output to the DisplayPort Source

HPD_ IN

15

I

Hot Plug Detect Input from the DisplayPort Connector

CABLE ADAPTER DETECT PINS

CAD _OUT

12

O

Cable Adapter Detect Output to the DisplayPort Source

CAD _ IN

14

I

Cable Adapter Detect Input from the DisplayPort Connector

CONTROL PINS

LP

33

I

Low Power Select Bar

CAD_INV

31

I

Output Port Priority selection

17

I

DisplayPort Main Link Output Gain Adjustment

NC

16

Not Connected

SUPPLY AND GROUND PINS

VCC

4, 16, 24, 28, 36

Primary Supply Voltage

VDD

10

HPD and CAD Output Voltage

GND

1, 7, 13, 21, 27, 32

Ground

Table 1. Control Pin Lookup

SIGNAL

STATE

DESCRIPTION

H

Normal Mode

Normal operational mode for device

LP

Device is forced into a Low Power state causing the outputs to go to a high impedance

L

Low Power Mode

state, All other inputs are ignored.

H

CAD Inverted

The CAD output logic is inverted from the CAD input

CAD_INV

L

CAD not Inverted

The CAD output logic follows the CAD input

4.53 k

Ω

Increased Gain

Main Link DisplayPort Output will have an increased voltage swing

6.49 k

Ω

Nominal Gain

Main Link DisplayPort Output will have a nominal voltage swing

10 k

Ω

Decreased Gain

Main Link DisplayPort Output will have a decreased voltage swing

(1)

(H) Logic High; (L) Logic Low

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