LFEC10 datasheet(28/163 Pages) LATTICE

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2-25

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-29. Output Register Block

Figure 2-30. ODDRXB Primitive

Tristate Register Block

The tristate register block provides the ability to register tri-state control signals from the core of the device before

they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for

DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block.

In SDR mode, ONEG1 feeds one of the ﬂip-ﬂops that then feeds the output. The ﬂip-ﬂop can be conﬁgured a D-

type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is

latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).

D-Type

ONEG0

From

Routing

CLK1

Programmed

Control

Latch

LE*

*Latch is transparent when input is low.

OPOS0

OUTDDN

/LATCH

To sysIO

Buffer

ODDRXB

LSR

CLK

LFEC10 bảng dữ liệu(PDF) 28 Page - Lattice Semiconductor