LFEC10 datasheet(13/163 Pages) LATTICE

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2-10

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

grammed during conﬁguration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after

adjustment and not relock until the tLOCK parameter has been satisﬁed. Additionally, the phase and duty cycle block

allows the user to adjust the phase and duty cycle of the CLKOS output.

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated

with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider

is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post

scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-

quency range. The secondary divider is used to derive lower frequency outputs.

Figure 2-11. PLL Diagram

Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.

Figure 2-12. PLL Primitive

VCO

CLKOS

CLKOK

LOCK

RST

CLKFB

from CLKOP

(PLL internal),

from clock net

(CLKOP) or

from a user

clock (PIN or logic)

Dynamic Delay Adjustment

Input Clock

Divider

(CLKI)

Feedback

Divider

(CLKFB)

Post Scalar

Divider

(CLKOP)

Phase/Duty

Select

Secondary

Clock

Divider

(CLKOK)

Delay

Adjust

Voltage

Controlled

Oscillator

CLKI

(from routing or

external pin)

CLKOP

EPLLB

CLKOP

CLKI

CLKFB

LOCK

EHXPLLB

CLKOS

CLKI

CLKFB

CLKOK

LOCK

RST

CLKOP

DDAIZR

DDAILAG

DDA MODE

DDAIDEL[2:0]

DDAOZR

DDAOLAG

DDAODEL[2:0]

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